1. Field of the Invention
The present invention relates to memories made in the form of an array network of memory cells in an integrated circuit. The present invention more specifically applies to DRAMs which store the data (states xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d) to be stored in memory cells, each formed of a storage capacitor and of a selection MOS transistor. Reference will be made hereafter to the example of a DRAM. It should however be noted that the present invention also relates to other types of memories, for example, SRAMs or EPROMs and, more generally, any array of cells.
2. Discussion of the Related Art
FIG. 1 very schematically shows an example of a cell 1 of a conventional DRAM. Such a cell 1 is formed of a selection MOS transistor T (herein, for example, an N-channel transistor) associated with a data storage capacitor C. The gate g of transistor T is connected to a row WL, called a word line. Drain d of transistor T is connected to a column line LBL, called a local bit line. Source s of transistor T is connected to a first terminal of capacitor C, the other terminal of which is connected to a constant voltage Vp, generally a median voltage (Vdd/2) between high and low supply voltages Vdd and Vss (generally the ground). Terminal s forms the storage node for the data of the memory cell thus formed. Several memory cells shown in FIG. 1 are associated in an array of word lines and bit columns.
For a cell 1 such as shown in FIG. 1 to be addressed., the word line WL associated with the gate of transistor T has to be brought to a high voltage, generally high supply voltage Vdd of the array.
If this addressing is linked to a write operation, storage node s is then placed either at the low supply voltage (Vss) of the array if capacitor C is discharged via a bit line LBL connected to the ground, or at potential Vdd if bit line LBL is placed at potential Vdd, signifying a programming to the high state. To simplify the present discussion, the levels described hereabove do not take account of the influence of threshold voltage Vt of transistor T upon the level stored in capacitor C.
If cell 1 is addressed in the read mode, local bit line LBL is precharged to a median potential (Vdd/2) between the two high and low supply potentials Vdd and Vss of the circuit. The stored state xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is then determined by comparing the potential of bit line LBL, modified according to the charge of capacitor C, with a reference bit line, also precharged to a level Vdd/2 but not influenced by the storage capacitor.
FIG. 2 very schematically illustrates the use of reference bit lines in a so-called xe2x80x9copenxe2x80x9d DRAM, in which the reference lines come from a neighboring array of memory cells, distinct from the array containing the addressed cell, as opposed to xe2x80x9cfoldedxe2x80x9d memories where the reference line of an addressed cell is formed by the bit line neighboring this cell. The present invention however also applies to folded memories as will be seen hereafter.
In such a memory architecture, a first plane or section P1 of cells 1 of the type shown in FIG. 1 is separated from a second memory plane P2 containing the same type of elementary cells 1xe2x80x2. Each plane P1, P2 forms by itself an array of memory cells independent from the other, in that it is addressable by different word lines WL1, WL2. On the bit line side, each memory plane has its own local bit lines LBL1 and LBL2, but shares the read/write or column decoding amplifiers (not shown in FIG. 2) with the other memory plane. Hereafter, reference will be made to a read amplifier or column decoder. In practice, each local bit line LBL1J or LBL2J of each memory plane P1, P2, is connected, via a section selection transistor Ts1j, Ts2j, to a global bit line GBL1, GBL2, respectively. Global bit lines GBL1j and GBL2j corresponding to columns of the same row j in the two memory planes P1 and P2, they however share a same column decoding amplifier, one of the two lines being used as a reference by the other. Accordingly, memory planes P1 and P2 are not addressed simultaneously in the read mode (this is why they are respectively associated with different word lines), each plane being in turns used as a reference plane for the memory cells read in the other memory plane.
For simplification, memory planes P1 and P2 have not been completely shown in FIG. 2. Only one cell for each plane and the section decoding transistor associated with the corresponding local bit line have been shown. The rank of the word lines has been designated by index I while the rank of the bit lines has been designated by index j.
Section selection transistors Ts1j and Ts2j receive, on their respective gates, control signals Seg1 and Seg2 which are simultaneously activated.
Assuming a reading of cell 1 at the intersection of lines WL1I and LBL1j, the selection transistor T of this cell is turned on, as well as the transistor Ts1j of selection of the section corresponding to memory plane P1. Global bit line GBL2j is then used as a reference bit line for the reading from cell 1 of plane 1, transistor Ts2j being also turned on to equalize the parasitic elements. The global bit lines are precharged to level Vdd/2 by means of precharge devices (not shown) connected, for the occasion, to first end terminals PL1j, PL2j of lines GBL1j, GBL2j. This precharge may be performed via local bit lines (all transistors Ts being on along the column). Since both global bit lines are precharged to level Vdd/2, the direction of the slight difference (coming from capacitor C of the decoded cell) between their respective levels during the reading determines the state of cell 1.
It should be noted that signals Seg1 and Seg2 simultaneously control the section selection transistors Ts1 and Ts2 of all the local bit lines of the memory plane with which these control signals are associated. The column selection in the memory array is generally performed downstream, that is, at the level of the data input-output stages in the memory. These stages (not shown in FIG. 2) especially include buffers.
FIG. 3 very schematically shows a conventional example of the read amplifier or column decoder CDEC and of an input-output stage I/O of a memory to which the present invention relates.
Each pair of global bit lines GBL1j, GBL2j, associated to be respectively used by the other as a reference bit line, is sent onto one of the two inputs of a column decoding amplifier Aj, intended for providing, on an output Sj, the decoded state of the memory cell from which it has been read. Amplifier Aj receives control and supply signals generally designated by reference CTRLj. Output Sj of amplifier Aj is sent, with the respective outputs of several other read amplifiers (for example, Aj+1), onto an input-output stage I/Oj for selecting one of the inputs that it receives to provide a single bit Bj which has been read. Stage I/Oj is controlled by a bit decoding circuit BDec, and is associated with several other input-output stages receiving output signals from different read amplifiers, each stage I/O providing a bit of a word (for example, of 16 bits) of the memory.
The bulk of a column decoding amplifier Aj of a conventional DRAM generally leads to having these amplifiers aligned two by two in the column direction to have a sufficient width to ensure all the connections required by the transistors constitutive of these amplifiers. Thus, in FIG. 3, two amplifiers Aj and Aj+1 have been shown to be aligned in the column direction (vertical direction in the drawing).
A problem which is raised in the making of DRAMs is the necessary compromise between the signal-to-noise ratio received by the column decoding amplifiers CDEC (FIG. 3) and the number of necessary section decoders SDEC (FIG. 2), and thus of memory planes P. Indeed, the higher the desired signal-to-noise ratio for the read amplifiers, the more the number of memory planes and, accordingly, the number of section decoder and read/write amplifiers, has to be increased.
It can be assumed that the signal-to-noise ratio variations are essentially due to the capacitors involved. Upon reading from a memory cell, two xe2x80x9cstrayxe2x80x9d capacitances intervene in addition to capacitor C of the cell. These originate, on the one hand, from global bit line GBL on which local bit line LBL of the cell from which it has been read connects, and which generally has a capacitance on the order of 450 fF. A second stray capacitance comes from local bit line LBL of the involved cell and depends on the number of cells connected on transistor Ts of the corresponding section decoder. Conventionally, for 64 connected cells per section, this local bit line capacitance is on the order of 150 fF. The stray capacitances are to be compared with the capacitance of capacitor C of the cell which is, for example, on the order of 35 fF. Such a 35 fF capacitance corresponds to the capacitance of a DRAM cell made in HCMIOS6 technology and of a size corresponding to the minimum size which can be made in this type of technology. Indeed, the capacitance of capacitor C of the memory cell is linked to its size, which is desired to be as small as possible to minimize the size of integrated circuit memories.
Signal-to-noise ratios smaller than {fraction (1/15)} are thus frequent, which results in a need for very high performance amplifiers Aj and, accordingly. for amplifiers including a relatively large number of transistors (on the order of some thirty transistors per amplifier).
Further, from a given threshold of the signal-to-noise ratio, and thus of the number of sections for a same amplifier, the memory has to be divided and the number of amplifiers must be multiplied.
To avoid further alteration of the signal-to-noise ratio, it is not conventionally desired to increase the number of cells per section.
However, a disadvantage of section decoders is that they are bulky and require control signals. Further, all section decoders have to be simultaneously controlled during the precharge of the global bit lines. Such a control results in a relatively strong current requirement with respect to the current required for the addressing of a word line. A consequence is the relatively long time taken at the level of a charge pump circuit to provide the sufficient current, unless said circuit is oversized, which adversely affects the memory size.
The space required to make the section decoders and the column decoding amplifiers determines, mainly with the bulk of the actual memory planes, the general bulk of the integrated circuit memory.
FIG. 4 very schematically illustrates the arrangement of the different elements constitutive of an integrated circuit DRAM of the type to which the present invention applies. The representation of FIG. 4 indicates the areas in which the different memory components are implanted on an integrated circuit chip 2.
For simplification, only six memory planes P1, P2, P3, P4, P5, P6 have been shown in FIG. 4. It should be noted that, in practice, the number of memory planes is much greater (on the order of 16, 32, and more). At one end of the word lines (not shown in FIG. 4) of each memory plane, a row decoder RDEC, associated with the memory plane involved, selects the addressed word line in the corresponding plane. The memory planes are associated two by two with a section decoder SDEC12, SDEC34, SDEC56 for selecting that of the memory planes, the local bit lines of which have to be used as a reference to read the other one. The global bit lines coming from the different section decoders are sent to the respective inputs of column decoding amplifiers CDEC, the respective outputs of which are sent to the inputs of input-output stages I/O.
The internal structure of the memory planes, of the section decoders, and of the input-output stages, as well as their operation, correspond to the above description of FIGS. 1 to 3. Row decoders RDEC are connected to a predecoder PREDEC receiving an address signal ADD over several bits. The input-output states I/O are connected to a data bus DATA over several bits and a control area CONTROL of the memory circuit receives control signals CTR. The control area is physically implanted in a corner of chip 2, left free after implantation of the other components, for example, in the lower left-hand corner of the chip, as illustrated in FIG. 4.
The memory planes and the section decoders altogether form what is generally called a memory array. The other circuits correspond to the decoding and input-output circuits of this array.
U.S. Pat. No. 5,499,215 discloses a memory in which column interconnection lines of sense amplifiers (SA) are connected by one end, to a column selection circuit (DA).
An object of the present invention is to provide a novel DRAM architecture which improves or optimizes the economy of space of the integrated circuit chip.
The present invention also aims at providing a DRAM which, for a given elementary memory cell size, has a reduced bulk with respect to conventional memories.
The present invention also aims at reducing or minimizing the current required for the memory operation, in particular, in the bit line precharge during a reading.
To achieve these and other objects, the present invention provides an integrated circuit memory including an array of memory cells divided into several sections, and several rows of column decoding amplifiers, the respective outputs of which are interconnected, by column, by means of a decoded bit line, each decoded bit line including two perpendicular parts, one of which is in the row direction to directly connect each decoded bit line to an input of an input-output stage of the memory arranged at one end of the rows.
According to an embodiment of the present invention, the direction change between the two parts is made without an active element, through a direct conductive interconnection.
According to an embodiment of the present invention, the memory includes one row of column decoding amplifiers for at most two sections.
According to an embodiment of the present invention, where each memory cell is formed of a transistor associated with a storage capacitor, each column decoding amplifier is directly connected to a local bit line interconnecting the respective drains of the transistors of the memory cells of a section.
According to an embodiment of the present invention, all the circuits of exploitation of the memory cells are housed in the same alignment on the integrated circuit.
According to an embodiment of the present invention, all the circuits of exploitation of the memory cells, except for the column decoding amplifiers, are housed on either side of the integrated circuit, at the ends of the memory cell rows.
According to an embodiment of the present invention, all the circuits of exploitation of the memory cells, except for the column decoding amplifiers, are housed on a single side of the integrated circuit, at one end of the memory cell rows.
According to an embodiment of the present invention, all the memory input-output buses are on a same side of the integrated circuit.
According to an embodiment of the present invention, the number of rows of memory cells per memory section is chosen to respect a signal-to-noise ratio in the read mode which is greater than {fraction (1/10)} at the input of the column decoding amplifiers.
The foregoing objects, features and advantages of the present invention, will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings.